In general, memory devices such as a flash electrically erasable programmable read only memory (EEPROM) are known. For example, referring to FIGS. 1, 2A, and 2B, a flash EEPROM 100, commonly comprises a single substrate 102 in which one or more high density core regions 104 and low density peripheral portion 106 are formed. Typical high-density cores 104 comprise at least one M.times.N array 104 of individually addressable, substantially identical memory cells 200 (FIGS. 2A and 2B). Low-density peripheral portions 106 normally include input/output (I/O) circuitry and circuitry for selectively addressing the individual cells. The selective addressing circuitry typically includes one or more x-decoders and y-decoders, cooperating with the I/O circuitry for connecting the source, the gate, and the drain of selected addressed cells to predetermined voltages or impedance to effect designated operations on the cell, e.g., programming, reading, and erasing, and deriving necessary voltages to effect such operations.
Referring now to FIGS. 2A and 2B, each cell 200 in core 104 includes a source 202, a drain 204, and channel 206 semiconductor regions formed in substrate 102 (or in an isolation well), and a stacked gate (word line) structure 210. Gate structure 210 suitably includes a thin gate dielectric layer 212 (commonly referred to as the "tunnel oxide") formed on the surface of substrate 102 overlying channel 206, a floating gate 214 overlying tunnel oxide 212, an interpoly dielectric 216 overlying floating gate 214, and a control gate 218 overlying interpoly dielectric layer 216. Cells 200 are arranged in a series of rows and columns.
In the completed array, the control gates 218 of the respective cells 200 in a row are formed integral to a common word line (WL) associated with the row. Columns of cells are arranged such that adjacent cells in a column share a common semiconductor region as source or drain regions. The source 202 of each cell in a column (excepting end cells) is formed in a common region with one of the adjacent cells, e.g., the preceding cell in the column. Likewise, the drain of one cell is formed in a common region with the drain 204 of the other adjacent cell, e.g., next succeeding cell in the column. The drain of each cell in a column of cells is connected by a conductive bit line (BL) (FIG. 2B) including an overlying layer of metal connected to each drain 204 of the cells 200 within the column. Additionally, the sources of each cell 200 in a row (and hence pairs of rows) are interconnected by a common source line CS (FIGS. 2A, 2B) formed in substrate 102, as will be described. Any particular cell 200 within array 104 can be individually addressed (programmed and read) by operating upon one word line and one bit line.
Typically, in forming an EEPROM 100, a pattern of field oxide regions 220 is initially formed to provide electrical isolation between the respective devices of memory device 100. For example, field oxide regions 220 are used to provide isolation between core array 104 and the devices of peripheral region 106, as well as between the various columns of cells 200 within core array 104. Field oxide regions are conventionally formed using a mask and selective growth process. A layer of thermal oxide ("barrier oxide" or "pad oxide") is grown or deposited over the surface of substrate 102. A mask, frequently composed of nitride, is deposited on the barrier oxide, and patterned to cover those regions of substrate 102 in which devices are to be formed (herein referred to as active regions). Field oxide is then grown in the exposed areas of the barrier oxide by, for example, local oxidation of silicon (LOCOS), and the masking layer and barrier oxide are stripped to expose the underlying substrate 102. In general, referring to FIG. 2A, within the core 104, the selective growth process results in alternating parallel strips of field oxide 220 and exposed regions corresponding to the columns of cells 200 in the array.
Stacked gate word line structures 210 are then typically formed. For example, tunnel dielectric 212, suitably including a thin (e.g., approximately 100 angstroms) layer of oxide, is initially formed on substrate 102 by a suitable technique, such as, for example, thermally oxidizing the surface of substrate 102 or by depositing a suitable material on substrate 102. A layer of suitable conductive polysilicon (e.g., polycrystalline silicon), that will ultimately form floating gates 214, is then formed on tunnel dielectric 212. For example, conductive polysilicon may be deposited by any suitable technique, e.g., conventional chemical vapor deposition (CVD). The polysilicon layer is typically then masked and etched to remove strips overlying field oxide regions 220, leaving isolated strips of polysilicon on top of tunnel dielectric 212 overlying the substrate regions corresponding to the columns of cells 200 of array 104 (i.e. the regions in which source, channel, and drain regions of cells in the column will be formed). A layer of suitable dielectric material, such as, e.g., an oxide-nitride-oxide (ONO) layer, that will ultimately form interpoly dielectric 216 is typically then formed by a suitable technique. For example, where interpoly dielectric 216 is ONO, it is suitably formed by growing a layer of oxide, depositing a layer of nitride, followed by growing a layer of oxide, depositing a layer of nitride, followed by growing another layer of oxide. Interpoly dielectric layer 216, in the completed array, insulates control gates 218 from floating gates 214 in the individual cells and electrically isolates the adjacent columns of floating gates 214 in array 104. Another layer of suitable conductive polysilicon (e.g., polycrystalline silicon), that will ultimately form control gates 218 (and word lines WL connecting the control gates of the cells in the respective rows of array 104) is then deposited on the interpoly dielectric layer, by a suitable technique, such as, for example, by conventional chemical vapor deposition (CVD). If desired, a silicide layer (not shown) may be provided over polysilicon layer 218 to reduce resistance. Portions of the respective polysilicon and interpoly dielectric layers are then selectively removed to define stacked gate structures 210 on tunnel dielectric layer 212, i.e., to form the floating gates 214, interpoly dielectric layer 216 and control gates 218 of the individual cells, and word lines WL (portions of interpoly dielectric 216 and control gate polysilicon layers, bridging field oxide regions 220, to connect the respective cells of the rows of the array). This is typically effected by suitable masking and etching techniques. When completed, the etch creates respective generally parallel word-line structures 210 separated by a distance D.sub.WL, as depicted in FIG. 2A.
Conventionally, the portions of field oxide 220 and tunnel dielectric 212 between every second pair of adjacent word lines 210 in array 104 (i.e., the regions, generally indicated as 222, where source regions 202 are to be formed and the portions of field oxide 220 disposed between source regions 202 of the corresponding cells of adjacent columns) are then removed, in preparation for formation of the common line (CS, FIG. 2A) connecting the sources. This is typically effected using a conventional self-aligned source etch (SAS). As will be discussed, the selective etch, however, normally removes not only the exposed field oxide regions 220, but also the exposed tunnel oxide 212, a portion of the exposed polysilicon, and a portion of the underlying substrate 102.
In a conventional process, source 202, common line CS, and drain 204 regions are then formed. Source 202 and common source line CS are formed by initially effecting a conventional double diffusion implant (DDI), with the SAS mask still in place. The DDI implants a first dopant (e.g., n-type), suitably phosphorous, to form a deeply diffused but lightly doped N well 202A (FIG. 2A), establishing a graded source-channel junction. The SAS mask is then removed. The DDI implant is typically driven deeper into substrate 102, by subjecting substrate 102 to a thermal cycle at high temperature (e.g., 1050 degrees Celsius). A shallow second implant, commonly referred to as a medium diffused drain (MDD) implant, is then performed (e.g., with arsenic) to create a more heavily doped, but shallower, n+ well 202B embedded within deep N well 202A. The MDD implant also forms a shallow, abrupt drain 204.
Conventionally, periphery transistors, passivation layers, and conductive interconnect layers (formed of, for example, polysilicon or metal) are then formed. The entire device is oxidized to form a sealing layer of silicon dioxide (not depicted) and finished and packaged for distribution.
Current is selectively conducted between source 202 and drain 204 in accordance with the electric field developed in channel 206 by gates 214, 218. By appropriately charging (programming) and discharging (erasing) floating gate 214, the threshold voltage V.sub.T of cell 200 (i.e., the voltage V.sub.G that must be applied to control gate 218 to cause current flow between source and drain above a predetermined level) may be selectively varied to program cell 200.
An individual cell 200 is programmed by charging floating gate 214 through high energy electron injection, often referred to as hot electron injection. By applying the appropriate potentials to source 202, drain 204, and control gate 218, hot electrons are injected from channel 206 through tunnel dielectric 212 to negatively charge floating gate 214. Charging floating gate 214 with a negative potential raises the threshold voltage of the cell by a predetermined mount V from a first nominal value V.sub.T1 to a second nominal value V.sub.T2. As a result, a programmed cell 200 (V.sub.T &gt;V.sub.T2) conducts substantially less current during a subsequent read operation than an unprogrammed cell 200 (V.sub.T &lt;V.sub.T1) having no charge on floating gate 214.
During a read operation, a predetermined voltage V.sub.G is applied to control gate 218 of selected cell 200. If the selected cell 200 is unprogrammed (V.sub.T &lt;V.sub.T1), the gate voltage V.sub.G exceeds the threshold voltage V.sub.T1 of the cell, and cell 200 conducts a relatively high current (above a predetermined upper threshold level, e.g., 100 microamps). Conduction of such high level current is indicative of the first state, e.g., a zero or logical low. On the other hand, if the selected cell 200 has been programmed (V.sub.T &gt;V.sub.T2), gate voltage V.sub.G is less than the threshold voltage V.sub.12 of the cell, and the cell is non-conductive, or at least conducts less current (below a predetermined lower threshold level, e.g. 20 microamps). Conduction of such low level current is indicative of a second state, e.g., one or logical high.
In contrast to the programming procedure, flash EEPROM's are typically bulk-erased, so that all of the cells 200 in array 104 (i.e., connected to a common source line CS) are simultaneously erased. Appropriate potentials applied to the source 202, drain 204 and control gate 218, cause electron tunneling from floating gate 214 to source 202 (or drain 204) via Fowler-Nordheim (F-N) tunneling. For example, electrons stored during programming on floating gate 214 tunnel through dielectric 212 in the area (referred to as a tunnel region 203) where floating gate 214 overlaps source region 202. F-N tunneling occurs simultaneously for all cells 200 within memory array 104, erasing entire array 104 in one "flash" or operation.
Because each cell 200 is connected to common source line CS, all cells 200 in array 104 are erased for the same amount of time. Ideally, each cell 200 in array 104 requires the same amount of time to erase, i.e. to remove electrons from floating gate 214 and achieve a lower selected threshold voltage. Erase times among cells 200 within array 104, however, differ widely. Because of the variation in erase times, each cell 200 must be erased for the amount of time required to erase the slowest cell in array 104. Erasing faster cells 200 for too long, however, results in over-erasure. Over-erasure generates a positive charge on floating gate 214, which excessively lowers the threshold voltage V.sub.T of cell 200, in some instances to the extent of establishing a negative threshold voltage (V.sub.T &lt;0). As a result, the over-erased cell 200 may be continuously activated, even when control gate 218 is grounded (V.sub.G =0 volts), so that cell 200 always conducts during a read operation, regardless of whether over-erased cell 200 is the cell selected for reading. In addition, the increase V in threshold voltage effected by programing, may not be sufficient to raise the threshold voltage V.sub.T of the over-erased cell above the predetermined voltage V.sub.G applied to control gate 218 of selected cell 200, so that even when programmed, the over-erased cell conducts upon application of V.sub.G during the read process, giving an erroneous reading.
The current conducted by over-erased cells 200 in a column during a read operation is known as "column leakage current". Column leakage current manifests itself by degrading or destroying the memory's reliability and endurance. As discussed above, the bit value of a selected cell 200 depends on the magnitude of the drain current provided at the associated bit line BL. Drain 204 of each cell 200 in a column, however, is connected to the associated bit line BL. Ideally, the only cell in the column biased for possible conduction is the cell in the selected word line WL; the predetermined voltage V.sub.G is applied to the gates of cells on the selected word line and all other gates are grounded during the reading process. If selected cell 200 is unprogrammed, current in excess of the upper threshold value will be provided on the bit line, indicating e.g., a zero. If the selected cell is programmed, with a "1", the drain current of the cell (and, ideally, the bit line), is below the lower threshold value during the read operation. However, the current in the bit line reflects the cumulative current flow from all of the cells in a column. Accordingly, if any of the cells in the column are over-erased and conduct significant current during the read operation, the current flow in the bit line may be in excess of the upper threshold value. Consequently, the read operation generates a logical zero regardless of which cell in the column is selected or whether the selected cell is programmed. In a severe case, a single over-erased cell will disable the entire column. In another case, many of the cells may be slightly over-erased which provides a cumulative column leakage current in excess of the upper threshold value. For example, if each cell in a column of 512 cells leaks 0.2 microamps, the total column leakage current is 102.4 microamps, in excess of the upper threshold value of 100 microamps, thereby disabling the entire column. Milder cases may simply degrade the performance of the memory over time, greatly reducing the reliability and endurance of the device, i.e., the number of cycles the device can be successfully programmed and erased.
It has been found that the disparity of erase times in conventional EEPROM cells 200 within array 104 is caused, at least in part, by structural and doping variations among cells 200. For example, the erase time cell 200 is affected by the F-N tunneling rate through tunnel dielectric 212, which, in turn, varies inversely with the square of the distance between floating gate 214 and source 202 in tunneling region 203 and varies directly with the doping concentration of tunneling region 203 near source 202, and specifically at the surface of channel 206. The geometry of each cell 200 near tunneling region 203, however, is difficult to control without significantly increasing the size of each cell. For example, as noted above, in forming memory devices a Self-Aligned Source (SAS) etch is typically used to remove the portions of field oxide 220 disposed between source regions 202 of the corresponding cells of adjacent rows (hereinafter referred to as the "inter-source" field oxide regions). Such an etch often causes variations in the geometries of the individual cells. Referring to FIGS. 3A-3C and 4A-4B, a masking layer of photo resist 302 is deposited over array 104, then patterned to mask (cover) drain regions 204 and the field oxide regions 220 isolating the drains of cells in adjacent columns, with open strips 304 exposing the source regions 202 of the corresponding cells of adjacent rows and the inter-source portions of field oxide 220; openings 304 have edges 306 disposed along the centers of the word lines 210 of adjacent rows of cells. A highly selective etch is then performed to remove the exposed portions of field oxide 220.
While the etch is highly selective in that it etches the field oxide at a much higher rate than the polysilicon word line or silicon, it is not totally selective; portions of the silicon of source region 202, as well as portions of the exposed polysilicon, are etched away. Referring to FIGS. 3A and 3B, the portions of tunnel dielectric 212 overlying the portions of substrate 102 where source regions 202 are to be formed are exposed by openings 304, as well as the inter-source portions of field oxide 220. The etch operates upon tunnel oxide 212 at the same rate as field oxide 220. Field oxide 220 is typically considerably thicker (e.g., 4000-5000 Angstroms) than tunnel oxide 212 (e.g., 100-200 Angstroms). By the time the inter-source portions of field oxide 220 are removed, not only has the etch removed the gate oxide 212 overlying the source region, but, as seen in FIG. 3A, it has also removed a portion of the silicon substrate 102 in the source region, producing a gouge of depth D.sub.G typically on the order of 200 Angstroms, in upper surface 308 of source region source 202. The depth D.sub.G of the gouge in source region 202 and the profile of surface 308 significantly affect the diffusion of dopants into tunneling region 203. In particular, the gouge increases the distance through which the dopants must travel to extend to the surface of channel 206, as depicted in FIG. 2A. Consequently, the gouge in surface 308 tends to decrease doping concentration in source 202 in tunneling region 203 when compared to an ungouged surface. Significantly, the gouging varies from cell to cell, creating non-uniformity.
Further, as seen in FIGS. 3A and 3B, a portion 310 of the exposed area of word line 210 is also etched away. This leads to the creation of a longitudinal step of depth D.sub.G2 typically on the order of 400 Angstroms, on the source side of the control gates 218 of the respective cells. This tends to increase the resistance of the word line 210.
Moreover, referring to FIGS. 3C and 4B, the etching process typically does not produce a vertical edge where field oxide 220 is removed. Rather, the process tends to produce sloping edges 412, extending outwardly from the edge of word line 210. Sloping edges 412 tend to constrict the portion 414 of substrate 102 exposed for implantation in the vicinity of field oxide 220. Thus, the width of common source line CS connection adjacent source regions 202, tends to be less than the distance D.sub.WL between respective adjacent word lines (the length of the source regions), and the resistance of the common source line CS is increased as compared to a wider region. In conventional memory arrays, such resistance is in the range of from 150 to 1000 ohms per bit. For example, the common source line CS of a memory array created using an SAS etching process may present a 3 square resistance structure (length in direction of current flow to width ratio), equating to approximately 180 ohms per bit.
For miniaturization, it is desirable to dispose adjacent word lines as closely together as possible, i.e., minimize distance D.sub.WL. The constriction of source line CS connecting adjacent source regions 202 by sloping edges 412 (and concomitant increased resistance), tends to be a limiting factor in miniaturization.
As an alternative to conventional self-aligned source technology, U.S. Pat. No. 5,656,513 (hereinafter the '513 patent), describes a mechanism to avoid the problems introduced by a self-aligned source etch process without sacrificing the advantages of self-aligned source technology. Rather than performing a self-aligned source etch to remove the field oxide to facilitate forming the connection between adjacent source regions, a field oxide layer is left intact, and a high energy implantation process is employed in conjunction with a self-aligned source mask to form the inter-source connection. The method described in the '513 patent uses a sufficiently high dose of dopants implanted at a sufficiently high energy level to cause the dopant to pass through the inter-source field oxide regions and locate within a predetermined region in substrate 102 to form low resistivity source interconnection regions underlying field oxide regions 220, thereby electrically connecting adjacent source regions.
Both conventional self-aligned source etching and the methodology described in the '513 patent have the disadvantage of allowing transient enhanced diffusion to occur to the DDI profile as a result of the low voltage source implantation step and the self-aligned source etching step. The implantation of dopants and self-aligned source etching can cause molecular damage to the silicon substrate that can enhance diffusion of the dopant. Current size restraints require the semiconductor device be manufactured using shallow pn junctions. The use of shallow junctions allows the damage caused by the implantation and the etching to remain near the junction, which results in high junction leakage currents. The transient enhanced diffusion of the dopants significantly effects the performance of the semiconductor device, and particularly with EEPROM memory devices, the diffusion can affect the erase rates of memory devices. Consequently, a need exists for a method for forming and connecting active regions and components of a high density semiconductor device wherein the erase rates of the device are not sensitive to the etching conditions used to form the connections.